Verilog HDL: Digital Design and Modeling Review

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(More customer reviews)I've been a fan or Mr. Cavanagh books beginning with his book "Digital Computer Arithmetic". Digital Computer Arithmetic: Design and Implementation (Computer Science) which I applied to an IC design I was working on (Philips 8051 derivative circa 1990). Now, I've found that I need to update my design skills and have a need to learn and apply the Verilog HDL language to apply to SDR radio design project ideas. This book fits that need. The book is not intended to be a tutorial on logic design. It is intended to be a tutorial on the complete Verilog language together with wide variety of design examples. The book begins with an overview of the Verilog language structure, language elements, and modeling concepts. Next the Verilog language elements, expressions, are covered followed by in-depth discussions of gate-level, dataflow, and behavioral, structural modeling. User-defined primitives, tasks, and functions are given apt attention. The book closes with addition design examples (a simple RISC CPU), and event queues. Note that the author uses the SILOS simulator for all examples. I found this to be an issue due to the cost of SILOS. However, a after a little research ending up with a quick trip to Wikipedia uncovered a nice low-cost Verilog design environment called LogicSim by Zeemz ([...]). Although I don't endorse any particular product, I've had no issues with LogicSim working my way thorough various portions of this book. I've also found that having a FPGA design kit (in my case a Xilinx Spartin-3 kit) is quite useful to apply the concepts. Your mileage may vary.
Note that if you are new to Verilog (but not to programming in general) the book is quite easy to read. Note that in order to fully grasp Verilog, in my opinion, you need to read the entire text (all 770+ pages) and work the examples. The explanation of Verilog is not condensed with follow-on project. The approach is to get you started with simple examples of what is presented in latter chapters. The various parts of Verilog are then covered in more depth. Some may not like this approach opting, instead, for a book that has complete projects on a specific kit (Xilinx Spartan 3, etc.). This is not the book for those individuals. There are plenty of books on Verilog. This book happens to fit my need to cover Verilog with, what I would describe, and "architectural twist". Mr. Cavanagh's other book complements this book.
The contents of the book are as follows:
Chapter 1 Introduction
Chapter 2 Overview
Chapter 3 Language Elements
Chapter 4 Expressions
Chapter 5 Gate-Level Modeling
Chapter 6 User-Defined Primitives
Chapter 7 Dataflow Modeling
Chapter 8 Behavioral Modeling
Chapter 9 Structural Modeling
Chapter 10 Tasks and Functions
Chapter 11 Additional Design Examples
Appendix A Event Queue
Appendix B Verilog Project Procedure
Appendix C Answers to Select Problems


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Emphasizing the detailed design of various Verilog projects, Verilog HDL: Digital Design and Modeling offers students a firm foundation on the subject matter. The textbook presents the complete Verilog language by describing different modeling constructs supported by Verilog and by providing numerous design examples and problems in each chapter. Examples include counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and much more. The text also contains information on synchronous and asynchronous sequential machines, including pulse-mode asynchronous sequential machines.In addition, it provides descriptions of the design module, the test bench module, the outputs obtained from the simulator, and the waveforms obtained from the simulator illustrating the complete functional operation of the design. Where applicable, a detailed review of the topic's theory is presented together with logic design principles, including state diagrams, Karnaugh maps, equations, and the logic diagram. Verilog HDL: Digital Design and Modeling is a comprehensive, self-contained, and inclusive textbook that carries all designs through to completion, preparing students to thoroughly understand this popular hardware description language.

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The System Designer's Guide to VHDL-AMS: Analog, Mixed-Signal, and Mixed-Technology Modeling (Systems on Silicon) Review

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(More customer reviews)VHDL-AMS contains everything that a typical language does, like C. But it goes beyond that by solving equations for you. For instance, the AMS part can help you solve ordinary differential equations, which is different from other computer languages. I feel that the book describes the usage of the language without giving enough details. You will have to learn certain aspects of the VHDL-AMS through your colleagues or other technical papers. VHDL-AMS has enough material to justify more than one book. A typical computer language takes one book to explain. VHDL-AMS goes way beyond that. So, do not get frustrated if you cannot learn everything from this book. With one single volume, it is just not feasible to cover everything.


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The demand is exploding for complete, integrated systems that sense, process, manipulate, and control complex entities such as sound, images, text, motion, and environmental conditions. These systems, from hand-held devices to automotive sub-systems to aerospace vehicles, employ electronics to manage and adapt to a world that is, predominantly, neither digital nor electronic.
To respond to this design challenge, the industry has developed and standardized VHDL-AMS, a unified design language for modeling digital, analog, mixed-signal, and mixed-technology systems. VHDL-AMS extends VHDL to bring the successful HDL modeling methodology of digital electronic systems design to these new design disciplines.
Gregory Peterson and Darrell Teegarden join best-selling author Peter Ashenden in teaching designers how to use VHDL-AMS to model these complex systems. This comprehensive tutorial and reference provides detailed descriptions of both the syntax and semantics of the language and of successful modeling techniques. It assumes no previous knowledge of VHDL, but instead teaches VHDL and VHDL-AMS in an integrated fashion, just as it would be used by designers of these complex, integrated systems. * Explores the design of an electric-powered, unmanned aerial vehicle system (UAV) in five separate case studies to illustrate mixed-signal, mixed-technology, power systems, communication systems, and full system modeling.* Includes a CD-ROM with code for all the examples and case studies in the book, an educational model library, a quick reference guide for VHDL-AMS, a syntax reference from Appendix E in the book, links to VHDL-AMS resources and Mentor Graphics SystemVision software, which provides a simulation and modeling environment with a schematic entry tool, a VHDL-AMS simulator, and a waveform viewing facility.

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SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling Review

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(More customer reviews)(My review is about the 2006 2nd-edition, not the older 1st edition!)
In general, I agree with the other reviews. This book is written for an audience of Verilog designers, who know the Verilog language (and its limitations) all to well. The book covers Systemverilog's new features like, enum, struct, interfaces, etc., from the perspective of "how to write better RTL-code using Systemverilog instead of Verilog.' For example, it explains the pros/cons of the (Systemverilog) "interface" construct, vs a flat group of (Verilog) module-port declarations. The discussion helps designers appreciate RTL-coding from a (slightly) higher levle of abstraction.
You don't need a specific background (i.e. design-engineer) to benefit from this book; you just need a good familiarity with conventional Verilog.
As others have said, this book is not suitable as a reference. The paragraphs flow well, but it's hard to lookup an arbitrary topic from the index. So far, no hardcover-book can displace the official IEEE Systemverilog LRM as the best reference.
And since the book focuses on the 'design' (synthesizeable) aspect of Systemverilog, it doesn't cover non-synthesizeable language features (like classes, constrained random variables, etc.)

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In its updated second edition, this book has been extensively revised on a chapter by chapter basis. The book accurately reflects the syntax and semantic changes to the SystemVerilog language standard, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter explaining the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

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